Methods for Synthesizing Program Intermediate Representations for the High-Level Design of Specialized Processors

P.N. Sovietov

Abstract


This paper discusses methods for automating the construction of software toolchains without explicit architecture descriptions at the early stages of designing specialized hardware accelerators. A formal model of an architecture-independent program intermediate representation is presented, along with a method for synthesizing an architecture-dependent representation based on the analysis of structural redundancy and similarity of target algorithm graphs. The resulting architecture-dependent representation, in the form of an architecture graph, can be used to automatically generate a software simulator and a compiler. A custom instruction synthesis method is developed, which includes the generation of literal fields and the semantic filtering of the set of synthesized instructions. Furthermore, the paper describes a method for constructing architectures of reconfigurable and programmable processors based on the problem of merging structurally similar algorithm graphs with resource generalization. This problem is reduced to a constraint programming model, which guarantees the absence of unwanted combinational loops in the hardware implementation. The evaluation of the proposed methods on cryptographic algorithms (AES, CRC32, Magma, SHA256) confirmed the feasibility of automatic architectural design space exploration to achieve the required trade-off between hardware resource utilization and processor performance.


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