Iterative compiler-based approach to synthesize and model a domain-specific instruction set

P. N. Sovetov


Processors with a domain-specific instruction set (ASIP, application-specific instruction set processor) are used today more and more widely. They are used in such areas as machine learning, image processing and cryptography. Due to the specialization of the architecture for solving problems from narrow domain areas the domain-specific processors can be more attractive than general-purpose processors in terms of, for example, characteristics such as energy efficiency. At the same time, due to the feature of programmability, domain-specific processors may be preferable to ASIC solutions.

One important task is to achieve a high developing speed of domain-specific instruction sets for solving problems from various domain areas. The paper proposes an iterative approach to the synthesis and modeling of a domain-specific instruction set based on the analysis of the dependency graph of the application at the basic block level, as well as using a set of architectural constraints. Basic RISC-like operations are combined into composite CISC operations. The parallelism of operations is revealed, including taking into account memory accesses, for instruction sets of VLIW type. For the practical evaluation of this approach, a compiler backend module has been developed. The results of synthesis and modeling of instruction sets for program tests selected from several domain areas are demonstrated.

Full Text:

PDF (Russian)


Elizarov G.S., Korneev V.V., Tarasov I.E., Sovetov P.N. Osnovnye tendencii razvitiya arhitektur specializirovannyh mnogoyadernyh processorov. OBZOR // Izv. vuzov. Elektronika. – 2018. – T. 23. – № 2. – P. 161–172. (in Russian)

Shafique M., Garg S. Computing in the dark silicon era: Current trends and research challenges //IEEE Design & Test. – 2016. – Т. 34. – №. 2. – С. 8-23.

Dean J., Patterson D., Young C. A new golden age in computer architecture: Empowering the machine-learning revolution //IEEE Micro. – 2018. – Т. 38. – №. 2. – С. 21-29.

Sovetov P.N. Avtomatizaciya proektirovaniya specializirovannyh processorov s ispol'zovaniem podhoda compiler-in-the-loop./Trudy XXII nauchnoj konferencii po radiofizike. – 2018. – P. 535. (in Russian)

Truong L., Hanrahan P. A Golden Age of Hardware Description Languages: Applying Programming Language Techniques to Improve Design Productivity //3rd Summit on Advances in Programming Languages (SNAPL 2019). – Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2019.

Willsey M. et al. Iterative Search for Reconfigurable Accelerator Blocks With a Compiler in the Loop //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2018. – Т. 38. – №. 3. – С. 407-418.

Zacharopoulos G. et al. RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2018. – Т. 38. – №. 4. – С. 741-754.

Van Praet J. et al. nML: A structural processor modeling language for retargetable compilation and ASIP design //Processor Description Languages. – Morgan Kaufmann, 2008. – С. 65-93.

Braun M., Buchwald S., Zwinkau A. Firm-a graph-based intermediate representation. – KIT, Fakultät für Informatik, 2011.

Click C., Cooper K. D. Combining analyses, combining optimizations //ACM Transactions on Programming Languages and Systems (TOPLAS). – 1995. – Т. 17. – №. 2. – С. 181-196.

Boulytchev D. BURS-based instruction set selection //International Andrei Ershov Memorial Conference on Perspectives of System Informatics. – Springer, Berlin, Heidelberg, 2006. – С. 431-437.

Pozzi L., Atasu K., Ienne P. Exact and approximate algorithms for the extension of embedded processor instruction sets //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2006. – Т. 25. – №. 7. – С. 1209-1229.

Nery A. S. et al. Automatic complex instruction identification for efficient application mapping onto ASIPs //2014 IEEE 5th Latin American Symposium on Circuits and Systems. – IEEE, 2014. – С. 1-4.

Haaß M., Bauer L., Henkel J. Automatic custom instruction identification in memory streaming algorithms //2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES). – IEEE, 2014. – С. 1-9.


  • There are currently no refbacks.

Abava  Absolutech Fruct 2020

ISSN: 2307-8162