Efficiency Improvement Approaches for a Mesh Network in a Distributed Memory System on Chip

Abstract

This paper studies architectural approaches to improving the efficiency of a mesh network in a distributed memory system on chip. The focus is on solutions applicable at early design stages, enabling analysis of trade-offs between network performance and hardware resource costs. The approaches include routing algorithm selection, network shape modification, scaling of physical and virtual channels, and duplication of the network infrastructure. Network efficiency is evaluated using throughput, average request latency, and performance per resource as the main metrics. Latency is estimated using an analytical model previously developed by the authors and tailored to distributed memory systems, while throughput is evaluated via cycle-accurate simulation. All approaches are compared within a unified experimental scenario, ensuring consistent assessment of their impact on traffic distribution, saturation behavior, and latency structure. The results show that the most efficient configurations improve traffic distribution with a moderate increase in hardware resources, whereas simple capacity scaling without structural changes leads to diminishing returns. The presented analysis provides practical guidance for selecting mesh network architectures in distributed memory systems at early design stages.